This invention relates to programmable logic devices ("PLDs"), and more particularly to bit line sense amplifiers for PLDs.
Programmable logic devices are well known. Such devices frequently take the form of an array of programmable interconnect elements (often referred to as "cells"). The array can be any size, including a single row, but it is not unusual for such an array to contain hundreds of rows and hundreds of columns. The array is based on a grid of orthogonal signal lines known as "bit lines" and "word lines." The programmable interconnect elements are typically erasable programmable read-only memories ("EPROMs"), such as electrically erasable programmable read-only memories ("EEPROMs") or ultraviolet erasable programmable read-only memories ("UVEPROMs"), although other types of programmable elements may be used. In a row of EPROMs extending in one direction, the gate of each EPROM is connected to a word line, while in an orthogonal row of EPROMs the drain of each EPROM is connected to a bit line. The source of each EPROM is connected to ground, typically through lines running parallel to the bit lines, although they could also run parallel to the word lines. The lines through which the sources are connected to ground, which may not actually be at ground potential, may be referred to as "common source lines," or just "source lines."
A user can "program" a desired bit in the array by placing a sufficient charge on the floating gate of the appropriate EPROM to prevent it from conducting even when its gate voltage (controlled by the word line) is high. Once the desired EPROMs have been programmed, a desired logical output can be obtained for a particular input to selected word lines.
One way of reading the output of the array is by sensing the status of each bit line with a circuit known as a sense amplifier, one of which is provided for each bit line. If none of the EPROMs connected to a particular bit line is conducting ("OFF"), the sense amplifier will indicate a high output. If any of the EPROMs is conducting ("ON"), it will tend to bring the bit line voltage to ground, resulting in a low output.
One tends to think of the EPROMs as switches, so that if any EPROM is conducting, the bit line should be shorted to ground. However, each EPROM has impedance and more importantly, capacitance, so that a conducting EPROM will have to discharge the capacitance of all of the non-conducting EPROMs connected to the same bit line. As a result, the bit line reaches ground faster if there are more EPROMs conducting (a state referred to as "super zero") than if only one is conducting ("weak zero"). Conversely, the transition from a super zero to a high state--i.e., from a state where many EPROMs are conducting to one where none is conducting--is also slow, because the capacitances of the EPROMs must be charged up from a relatively low initial potential, as compared to the transition from a weak zero state to a high state, where the capacitances of the same number of EPROMs must be charged, but from not quite so low an initial potential.
An OFF cell gives a voltage difference between the drain line and the source line large enough for the sense amplifier to sense and output a high. An ON cell gives a voltage difference between the drain line and the source line small enough for the sense amplifier to sense and output a low. The difference in potential between drain line and source line at which the sense amplifier can sense a transition of the state of the cell and make a transition in output state is known as the trip voltage. The speed of a sense amplifier depends on how close the voltage difference between the drain line and the source line is to the trip voltage. The trip voltage for the sense amplifier is the same for high-to-low and low-to-high transitions, except that they are reached from opposite directions.
Many existing sense amplifiers are triggered to output a high or low signal based simply on a particular voltage level on the bit line. These sense amplifiers thus switch more slowly from the high state to the weak zero state than the from high state to the super zero state, and from the super zero state to the high state than from the weak zero state to the high state, because of the difference in elapsed time necessary to reach the switching voltage from the different states.
A particularly effective way to increase the speed of each transition is to bias the voltage difference between the drain line and the source line closer to the appropriate trip voltage (i.e., for the ON-to-OFF transition or the OFF-to-ON transition, depending on the present state) by using feedback. The feedback must prepare the drain line and source line voltages for the upcoming transition, without affecting the previous transition.
The cost of using feedback to gain speed is a reduction of the sense amplifier circuit's immunity to variations in fabrication of the transistors in the device, and the device has reduced immunity to device switching noise. Depending on fabrication conditions, transistors can have higher or lower device conductivity. If the feedback transistors have too high conductivities (sometimes referred to as "strong processing"), feedback causes the sense amplifier to be more susceptible to noise. If the feedback transistors have too low conductivities (sometimes referred to as "weak processing"), the effects of feedback are not strong enough to allow the sense amplifier to switch at its maximum rate.
During normal operation, feedback is used to increase the transition speed. A low power mode provides lower power operation (and a slower transition speed) by causing the feedback and feedback stabilization circuitry to cease conducting, albeit at the cost of increase switching time.
It would be desirable to be able to provide a sense amplifier having switching times that are substantially the same regardless of the initial state of the cell.
It would also be desirable to be able to provide feedback circuitry for limiting the voltage swing on the bit line of a PLD to improve switching speed.
It would further be desirable to be able to provide circuitry for stabilization of the feedback circuitry and to counteract fabrication induced variations in device impedance.
It would still further be desirable to be able to provide a sense amplifier that can be selectively operated in a low power mode.